1. Field of the Invention
The present invention pertains to a semiconductor memory and more particularly to an improvement of a sense amplifier in a static RAM comprised of Bi-CMOS circuits within a semiconductor memory.
In a static RAM comprised of Bi-CMOS circuits, where a bipolar transistor and p-channel and n-channel MOS transistors are present in the same chip, steps are taken to minimize an oscillation of a potential level of a common data line, which oscillation is required to enable both the reading and writing operations, so that a shift between H level and L level that takes place in both directions on the common data line can be made faster.
2. Description of the Related Art
A description will now be given of a static RAM comprised of conventional Bi-CMOS circuits, with reference to FIGS. 1 and 2. FIG. 1 is a circuit diagram of a memory cell and a bit selecting means portion in a conventional static RAM. FIG. 2 is a circuit diagram of a conventional sense amplifier and an I/O portion thereof in a conventional static RAM. Referring to FIG. 1, this static RAM comprises a number of memory cells 11, 11' disposed in respective columns 33 and 33' and in respective rows. The memory cells 11 and 11' in the columns 33 and 33' are supplied with respective signal lines Xm and Xm' from respective word lines 20 and 20' in each row. When the signal lines Xm and Xm' are at a logical level "H", either of the memory cells 11 or 11' becomes connected to a pair of bit lines 25a and 25b disposed in each column.
Bit selecting means 32 and 32' are disposed in correspondence with each pair of bit lines 25a and 25b, and comprise a column switch consisting of two pairs of transistors; namely a pair of n-channel MOS transistors 8a, 9a and a pair of p-channel MOS transistors 8b, 9b, and further comprising bit line load transistors 10a and 10b consisting of p-channel MOS transistors. Each of the column switches 8a and 8b begins conducting in response to the logical level "L" of a column address Yn, and connects the corresponding pair of bit lines 25a and 25b to a pair of common data lines 26a and 26b. Also, the bit load transistors 10a and 10b begin conducting so as to connect the pair of bit lines 25a and 25b to a constant-voltage regulated power supply VRS (-0.8 V, for example) 22. After the column switches 8a and 8b begin conducting, the common data lines 26a and 26b connect one of the memory cells 11 or 11' selected in accordance with a column address and a row address to a sense amplifier.
Referring to FIG. 2, a sense amplifier 31 comprises: a differential amplifier constituting an ECL circuit, which amplifier allows the signals on the common data line 26a and 26b to be received at the bases of bipolar transistors 5a and 5b and outputs the amplified results as outputs 16a and 16b of the sense amplifier 31; a pair of write n-channel MOS transistors 4a and 4b constituting a write means for receiving an input of a signal consisting of a write signal and a write data, and connecting either of the common data lines 26a and 26b to a VEE power supply (-4.5 V, for example) 24 on the basis of the write data; data line load transistors 3a and 3b consisting of a pair of p-channel MOS transistors, which transistors conduct when the write transistors 4a and 4b are OFF, thus allowing connection between the VRS power supply 22 and each of the common data lines 26a and 26b, and supplying a read current to a memory cell at the read operation time.
Gates are disposed in the input portion of the sense amplifier 31; namely a pair of NOR gates 2a and 2b which receive an input of a write signal WE' (hereinafter WE' represents a WE having a top bar) at one of the terminals thereof, and a data input gate 1 which, upon receipt of a write data Din, feeds this write data and an inverted signal on the basis of the write data to the other terminal of the above-mentioned NOR gates 2a and 2b, respectively. The outputs from each of the NOR gates 2a and 2b are fed to the inputs of the gates of the write transistors 4a and 4b, and the gates of the data line load transistors 3a and 3b.
In the above static RAM, the write signal WE' is at an "H" level at the read operation time, prompting the output from the pair of NOR gates 2a and 2b constituting the input portion of the sense amplifier to be at a level "L", and turning each of the data line load transistors 3a and 3b on. In addition, a memory cell selected at the read operation time on the basis of a row address and a column address is connected to the pair of common data lines 26a and 26b. This description, which is given in accordance with FIG. 1 assumes that the memory cell 11 of the column 33 is the selected memory cell and that a driver MOS transistor 13a therein is ON in correspondence with the data stored in the memory cell 11.
The current from the data line load transistor 3a flows into the bit line 25a via the common data line 26a, and thus reaches the VEE power supply 24 via the driver MOS transistor 13a of the memory cell 11. As a result, due to a voltage drop in the data line load transistor 3a, the potential of this common data line 26a drops significantly. However, the other common data line 26b has the same potential as the power supply VRS 22 because there is no voltage drop in the data line load transistor 3b as the driver MOS transistor 13b is off. The differential amplifier consisting of the bipolar transistors 5a and 5b, load resistors 6a and 6b, and a constant-current regulated power supply 15 detects and amplifies the potential difference between these common data lines 26a and 26b, and outputs the result as the outputs 16a and 16b of the sense amplifier 31.
At the write operation time, the write signal WE' is brought to an L level. One of outputs 27a and 27b from, respectively, the NOR gates 2a and 2b is brought to an H level and the other output to an L level, on the basis of the write data Din. Assuming that this write data Din is at a logical "L" level, the output 27a will be at an H level and the output 27b will be at an L level; the data line load transistor 3a will be OFF and the data line load transistor 3b will be ON; and the write transistor 4a will be ON and the write transistor 4b will be off. As a result of the write signal WE' being at the L level, the n-channel MOS write column switches 9a and 9b, which constitute the column switch of the bit selecting means 32, will be ON and the bit line load transistors 10a and 10b will be off. The other column switch, namely the p-channel MOS transistor 8a, will be ON in response to the row address being at an L level.
As a result of the above, a write current flows into the VEE power supply 24 via a VCC power supply (0 V, for example) 23 of the memory cell, a memory cell load resistor 14a, a transfer MOS transistor 12a, the n-channel transistor 9a and the p-channel transistor 8a, which transistors constitute column switches, the common data line 26a, and the write transistor 4a. Further, the potential of the bit line 25a is lowered to be equal to that of the VEE power supply 24, which is approximately -4.5 V, for example. On the other hand, since the other write transistor 4b is OFF, the potential of the bit line 25b is approximately equal to that of the VRS power supply 22, for example, -0.8 V. The respective potentials of the bit lines 25a and 25b force the driver MOS transistor 13b of the memory cell 11 to be OFF, prompt the other driver MOS transistor 13a to be ON, and complete the write operation of Din. When the write data Din is at "H", the write operation is carried out in the same way as described above except that the respective bit lines potentials of the bit lines 25a and 25b force the driver MOS transistor 13a (not 13b) of the memory cell 11 to be OFF and prompt the other driver MOS transistor 13b (not 13a) to be ON.
In each column not selected on the basis of a column address, the n-channel and p-channel MOS transistors 8a, 9a, 8b, and 9b, which embody column switching means, are all OFF, wherein the bit lines relevant thereto are disconnected from the common data lines 26a and 26b, and the bit line load transistors 10a and 10b retain, by being turned ON, the data of the memory cell selected on the basis of the row address.
In the conventional static RAM described above, the bases of the bipolar transistors 5a and 5b constituting a differential amplifier of the sense amplifier have different potentials; that is, the base of one transistor is at approximately the same potential level as the VRS power supply 22, while the base of the other transistor is at a potential level lowered to be approximately equal to that of the VEE power supply 24. This difference in potentials leads to a problem in that a reverse voltage is applied across the emitter and base of the above other transistor. It is normally recommended that the E-B reverse withstand voltage of a transistor in an integrated circuit be maintained to be below 5 V. The more minute a mask pattern, the lower this voltage should be. It is known, for example, that, in an extremely minute mask pattern, this E-B reverse withstand voltage is approximately 2-3 V. A serious disadvantage of the conventional static RAM is that the above-mentioned reverse voltage exceeds the E-B reverse withstand voltage.
The magnitude of the E-B reverse voltage applied to the transistors of the above ECL circuit is represented by [VEE]-[VRS]-[V.sub.BE ] (where the parenthesis [] as in [VEE] signifies an absolute value). Taking into account that a forward base-emitter voltage drop V.sub.BE of a transistor is normally around 0.8 V, and assuming that the voltage value of each power supply has the value specified as examples in the forgoing discussion (VEE=-4.5 V, VRS=0.8 V), the reverse voltage across the emitter and base is 2.9 V. This value means that a problem may be expected in which the emitter-base reverse voltage could exceed an E-B reverse withstand voltage BV.sub.EB of a transistor in an integrated circuit having a minute mask pattern, and that transistors therein are liable to degradation in characteristics or permanent breakdown due to withstand breakdown. It is known that even when the emitter-base reverse voltage does not exceed the E-B reverse withstand voltage BV.sub.EB, some types of transistors, such as a polysilicon-base self-align transistor, are liable to degradation in characteristics, including a drop in a current gain h.sub.fe, due to a relatively large E-B reverse voltage. Accordingly, when using such a transistor, the emitter-base reverse voltage should not only be kept below the E-B reverse withstand voltage but also be kept as low as possible.
A static RAM comprised of Bi-CMOS circuits has a disadvantage in that the lower limits of the potential oscillation of the bit lines 25a and 25b and the common data lines 26a and 26b, are determined by the lowest detectable level of the sense amplifier. These lower limits of the potential oscillation are each approximately 50 mV, for example. Maintaining the potential oscillation at a low level irrespective of the lowest detectable level of the sense amplifier allows a speedy bilateral shift to each designated potential level of the common data lines and the bit lines, which lines have large incidental capacitance, so that a speed-up of a static RAM is achieved. Though this fact is known, the conventional static RAM has the above-mentioned limitation and therefore a speed-up thereof is to a certain extent limited.
Further, although a reduction of potential oscillation is actually achieved at the read operation time as described before, the potential level of the bit line 25a is lowered to the potential level of the VEE power supply, at the write operation time. It thus takes time to return from this potential level to the original potential level that is maintained at the read operation time, which return is realized by means of the data line load transistor 3a and the bit line transistor 10a. Failure to return to the original potential level before the next read cycle can affect an access time. In addition, a speed-up of a static RAM is thwarted.